AMD EPYC 'Rome': Zen 2 on 7nm, 64C/128T of CPU power

Joanna Estrada
November 8, 2018

Previously, a PC hardware analyst had predicted that AMD would attempt to move all IO functions of the CPU to a larger 14nm die (since IO usually benefits little from newer processes) and connect it to the 7nm CPU core die with Zen 2; he referred to this method of partitioning the CPU as "chiplets". If the claims hold up, the second-generation processor has a shot at being the highest performing datacenter CPU in 2019.

'Legacy GPU architectures limit IT managers from effectively addressing the constantly evolving demands of processing and analysing huge datasets for modern cloud data centre workloads, ' claims David Wang, senior vice president of engineering at AMD's Radeon Technologies Group.

At its Next Horizon event in San Francisco, AMD announced the fourth iteration of its Zen microarchitecture. That could soon change. Working under the codename Rome, the chip is claimed to offer considerable improvements in instructions-per-clock (IPC), the addition of PCI Express 4.0 connectivity, and a claimed doubling of performance-per-socket for traditional compute and quadrupling for floating-point operations compared to current-generation Epyc chips while retaining socket compatibility.

A little context: Intel's top-of-the-line 28-core Xeon Skylake processor now offers about three times the floating point performance of the first-generation 32-core EPYC 7601 processor.

Intel attempted to get ahead of the curve earlier this week, unveiling its 14nm 48-core Cascade Lake-AP Xeon processor for datacentres.

Are you a techie who knows how to write? Papermaster summed it up thusly: "We're in the business of high performance". New processors based on Zen 2 will use a 7nm manufacturing process and start hitting the market in 2019. When matched against a dual-socket Xeon Platinum 8180M server, the AMD box ran the benchmark to completion first.

According to AMD, the dedicated I/O die offers improved latency and power consumption for the new Epyc Rome processors.

Right now, the company is sampling its codenamed Rome CPUs based on Zen 2 microarchitecture and made using TSMC's first-generation 7 nm manufacturing technology (N7). But because of continued delays in Intel's 10nm effort, AMD lucked out; it will be shipping some of the fastest and most power-efficient silicon in the datacenter next year. There is a single 14nm I/O die, with eight memory controllers, with Infinity Fabric ports and PCIexpress lanes, and then 7nm chipset which handle the CPU tasks themselves. A Zen 4 processor is also in the works, although no timeline was given for its debut.

Other reports by Click Lancashire

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